Overcoming the Impact of Transistor Scaling
Join Applied Materials and guest speakers from across the industry at the Hotel Nikko, San Francisco, for a lively discussion of challenges facing interconnect technologies. Can they keep pace with transistor scaling and the transition to 3D architectures?
The 14 nm node is likely to be the inflection point beyond which copper resistivity increases exponentially. How will circuit design and system architecture be able to address future limitations in interconnect performance? How will the complexity of multi-patterning and EUV impact interconnect pitch scaling? Will current integration schemes continue to scale or be replaced?
Hear answers to these questions and more from some of today’s industry leaders.
Applied Materials looks forward to welcoming you!
Hotel Nikko, San Francisco
222 Mason Street
Nikko Ballroom, Third Floor
Tuesday, December 11, 2012
5:00 – 6:15 PM Registration and Reception
6:15 – 7:40 PM Panel Session
7:40 – 8:00 PM Beverages / Social
** To expedite the check-in process, please bring your business card and your IEDM conference badge with you to the event.